This invention relates to a semiconductor integrated circuit device (IC device), and more particularly to a package for a very high speed IC device.
In very high speed IC devices operating at a high frequency of a G Hz band such as a GaAs (gallium arsenide) IC device, a characteristic impedance of a signal transmission line for connecting electrically the IC device to another device must be matched with an impedance of a source of the signal carried by the signal transmission line. For, if the characteristic impedance of the signal transmission line carrying the high frequency signal does not match with the impedance of the source of the signal, a transmission loss such as reflection of the signal and distortion of a waveform occurs and a normal operation of the IC device is impeded. Therefore, a package accommodating therein a very high speed IC device is designed so that the value of the characteristic impedance of the signal line inside the package is in match with the value of the impedance of the signal source. As to an IC package for a very high speed IC device, refer to Japanese literature "HIGH DENSITY PACKAGING TECHNOLOGY HANDBOOK", published by Science-Forum Co., Ltd. (Mar. 15, 1986), pp. 352-353.
However, most of the conventional packages for very high speed IC devices do not consider sufficiently impedance matching of a bonding wire for connecting the signal line inside the package and the IC device or in other words, a semiconductor chip. For this reason, the transmission loss of the signal resulting from mismatching of the impedance of the bonding wire cannot be neglected as the operating frequency of the device becomes higher.
One of the semiconductor devices accommodating therein a semiconductor chip for handling a high frequency signal, which is disclosed in JP-A-63-22873 (laid-open on Sep. 22, 1988) has a coplanar structure in which ground lines are disposed, on the same plane, on both sides of one signal line both on a semiconductor chip and on a package so as to provide a desired characteristic impedance and bonding wires for connecting electrically the signal lines of the semiconductor chip and package with one another and those for connecting electrically ground lines of the semiconductor chip and package with one another are integrally fixed by a holding member of a dielectric material so as to keep constant the mutual gap and to provide the bonding wires with the same characteristic impedance as that of the signal line of the semiconductor chip and package.
JP-A-2-72654 (laid-open on Mar. 12, 1990) teaches provision of specific ones of the terminals of a package extending along the inner wall of a frame member defining a space for accommodating an IC chip and to connect it electrically to a stage of a metal on which the IC chip is placed inside the space in order to suppress cross-talk in the IC package.
JP-A-57-107059 (laid-open on Jul. 3, 1982) teaches to dispose ground conductors for surrounding the entire surface of an IC chip inclusive of its bottom and sides inside a package for accommodating the IC chip and thus to stabilize the operation of the IC chip against noise.